Unconventional transistor sizing for reducing power alleviates threshold voltage variations

Azam Beg, Valeriu Beiu, Walid Ibrahim

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)

    Abstract

    Digital circuits can be synthesized with only NANDs or NORs, while delay and power can be quite different. Scaling transistors increases their sensitivity to variations and in particular to threshold voltage variations (σVTH). Sizing transistors trades delay versus power, while unconventional sizing (e.g., L > Lmin, W/L < 1, fine-grained increments, multifinger FETs) was proposed recently for reducing power and also σVTH. Using Monte Carlo simulations we perform an analysis of how sensitive the output voltages of NAND-2 and NOR-2 are to increasing L over Lmin, and examine how such sizing affects delay, power, and power-delay-product of these two gates.

    Original languageEnglish
    Title of host publication2012 International Semiconductor Conference, CAS 2012 Proceedings
    Pages429-432
    Number of pages4
    DOIs
    Publication statusPublished - 2012
    Event35th International Semiconductor Conference, CAS 2012 - Sinaia, Romania
    Duration: Oct 15 2012Oct 17 2012

    Publication series

    NameProceedings of the International Semiconductor Conference, CAS
    Volume2

    Conference

    Conference35th International Semiconductor Conference, CAS 2012
    Country/TerritoryRomania
    CitySinaia
    Period10/15/1210/17/12

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Condensed Matter Physics
    • Electrical and Electronic Engineering

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