TY - GEN
T1 - Unconventional transistor sizing for reducing power alleviates threshold voltage variations
AU - Beg, Azam
AU - Beiu, Valeriu
AU - Ibrahim, Walid
PY - 2012
Y1 - 2012
N2 - Digital circuits can be synthesized with only NANDs or NORs, while delay and power can be quite different. Scaling transistors increases their sensitivity to variations and in particular to threshold voltage variations (σVTH). Sizing transistors trades delay versus power, while unconventional sizing (e.g., L > Lmin, W/L < 1, fine-grained increments, multifinger FETs) was proposed recently for reducing power and also σVTH. Using Monte Carlo simulations we perform an analysis of how sensitive the output voltages of NAND-2 and NOR-2 are to increasing L over Lmin, and examine how such sizing affects delay, power, and power-delay-product of these two gates.
AB - Digital circuits can be synthesized with only NANDs or NORs, while delay and power can be quite different. Scaling transistors increases their sensitivity to variations and in particular to threshold voltage variations (σVTH). Sizing transistors trades delay versus power, while unconventional sizing (e.g., L > Lmin, W/L < 1, fine-grained increments, multifinger FETs) was proposed recently for reducing power and also σVTH. Using Monte Carlo simulations we perform an analysis of how sensitive the output voltages of NAND-2 and NOR-2 are to increasing L over Lmin, and examine how such sizing affects delay, power, and power-delay-product of these two gates.
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U2 - 10.1109/SMICND.2012.6400739
DO - 10.1109/SMICND.2012.6400739
M3 - Conference contribution
AN - SCOPUS:84872870457
SN - 9781467307369
T3 - Proceedings of the International Semiconductor Conference, CAS
SP - 429
EP - 432
BT - 2012 International Semiconductor Conference, CAS 2012 Proceedings
T2 - 35th International Semiconductor Conference, CAS 2012
Y2 - 15 October 2012 through 17 October 2012
ER -