Using body bias when upsizing length for maximizing the static noise margins of CMOS gates

Fekri Kharbash; Valeriu Beiu; Mihai Tache; Walid Ibrahim

doi:10.1109/ICECS.2013.6815441

Using body bias when upsizing length for maximizing the static noise margins of CMOS gates

Fekri Kharbash, Valeriu Beiu, Mihai Tache, Walid Ibrahim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper uses body bias for improving on a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). The method leads to highly reliable gates, operating correctly over the whole voltage range. Besides calculating the threshold voltage (V_th) exactly (precise L's) and having more accurate SNMs (maximum square method), in this paper we shall use biasing (V_bs) for having a single L _opt for all transistors (as opposed to having two different L _opt, one for nMOS and another one for pMOS) leading to better manufacturability. Simulations for INV, NAND-2, and NOR-2 show that although V_th and L change by ∼10%, by using V_bs we can still achieve very high SNM's, while additionally reducing power and energy to ∼50%.

Original language	English
Title of host publication	2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	409-412
Number of pages	4
ISBN (Print)	9781479924523
DOIs	https://doi.org/10.1109/ICECS.2013.6815441
Publication status	Published - 2013
Event	2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013 - Abu Dhabi, United Arab Emirates Duration: Dec 8 2013 → Dec 11 2013

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Other

Other	2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013
Country/Territory	United Arab Emirates
City	Abu Dhabi
Period	12/8/13 → 12/11/13

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ICECS.2013.6815441

Cite this

Kharbash, F., Beiu, V., Tache, M., & Ibrahim, W. (2013). Using body bias when upsizing length for maximizing the static noise margins of CMOS gates. In 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013 (pp. 409-412). Article 6815441 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.2013.6815441

Using body bias when upsizing length for maximizing the static noise margins of CMOS gates. / Kharbash, Fekri; Beiu, Valeriu; Tache, Mihai et al.
2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013. Institute of Electrical and Electronics Engineers Inc., 2013. p. 409-412 6815441 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kharbash, F, Beiu, V, Tache, M & Ibrahim, W 2013, Using body bias when upsizing length for maximizing the static noise margins of CMOS gates. in 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013., 6815441, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 409-412, 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013, Abu Dhabi, United Arab Emirates, 12/8/13. https://doi.org/10.1109/ICECS.2013.6815441

Kharbash F, Beiu V, Tache M, Ibrahim W. Using body bias when upsizing length for maximizing the static noise margins of CMOS gates. In 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013. Institute of Electrical and Electronics Engineers Inc. 2013. p. 409-412. 6815441. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). doi: 10.1109/ICECS.2013.6815441

Kharbash, Fekri ; Beiu, Valeriu ; Tache, Mihai et al. / Using body bias when upsizing length for maximizing the static noise margins of CMOS gates. 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013. Institute of Electrical and Electronics Engineers Inc., 2013. pp. 409-412 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

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title = "Using body bias when upsizing length for maximizing the static noise margins of CMOS gates",

abstract = "This paper uses body bias for improving on a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). The method leads to highly reliable gates, operating correctly over the whole voltage range. Besides calculating the threshold voltage (Vth) exactly (precise L's) and having more accurate SNMs (maximum square method), in this paper we shall use biasing (Vbs) for having a single L opt for all transistors (as opposed to having two different L opt, one for nMOS and another one for pMOS) leading to better manufacturability. Simulations for INV, NAND-2, and NOR-2 show that although Vth and L change by ∼10%, by using Vbs we can still achieve very high SNM's, while additionally reducing power and energy to ∼50%.",

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N2 - This paper uses body bias for improving on a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). The method leads to highly reliable gates, operating correctly over the whole voltage range. Besides calculating the threshold voltage (Vth) exactly (precise L's) and having more accurate SNMs (maximum square method), in this paper we shall use biasing (Vbs) for having a single L opt for all transistors (as opposed to having two different L opt, one for nMOS and another one for pMOS) leading to better manufacturability. Simulations for INV, NAND-2, and NOR-2 show that although Vth and L change by ∼10%, by using Vbs we can still achieve very high SNM's, while additionally reducing power and energy to ∼50%.

AB - This paper uses body bias for improving on a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). The method leads to highly reliable gates, operating correctly over the whole voltage range. Besides calculating the threshold voltage (Vth) exactly (precise L's) and having more accurate SNMs (maximum square method), in this paper we shall use biasing (Vbs) for having a single L opt for all transistors (as opposed to having two different L opt, one for nMOS and another one for pMOS) leading to better manufacturability. Simulations for INV, NAND-2, and NOR-2 show that although Vth and L change by ∼10%, by using Vbs we can still achieve very high SNM's, while additionally reducing power and energy to ∼50%.

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Using body bias when upsizing length for maximizing the static noise margins of CMOS gates

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