TY - JOUR
T1 - VLSI Implementations of Threshold Logic - A Comprehensive Survey
AU - Beiu, Valeriu
AU - Quintana, José M.
AU - Avedillo, María J.
N1 - Funding Information:
Lastly, because nano (and reconfigurable) computing will probably get center-stage positions in the (near) future, TL will surely benefit from that. As RTDs are already operating at room temperature (as opposed to SET), they appear to hold the most promise as a short-to-medium-term solution. The fact that TL is a perfect fit for RTDs will certainly help. This trend is proven by many projects funded by the NSF.
Funding Information:
Manuscript received September 15, 2002; revised May 24, 2003. The work of V. Beiu was supported in part by the Air Force Research Laboratory under Agreement F29601-02-2-0299. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon. The views and conclusions contained herein are those of the author and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the Air Force Research Laboratory or the U.S. government. The work of J. M. Quintana and M. J. Avedillo was sponsored in part by the EU under IST 2001–32358 Project “QUDOS.” V. Beiu is with the School of Electrical Engineer and Computer Science, Washington State University, Pullman, WA 99164-2752 USA (e-mail: vbeiu@eecs.wsu.edu).
PY - 2003/9
Y1 - 2003/9
N2 - This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.
AB - This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.
KW - Integrated circuits
KW - Neural-network (NN) hardware
KW - Threshold logic
KW - Very-large-scale integration (VLSI)
UR - http://www.scopus.com/inward/record.url?scp=0141485506&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0141485506&partnerID=8YFLogxK
U2 - 10.1109/TNN.2003.816365
DO - 10.1109/TNN.2003.816365
M3 - Review article
C2 - 18244573
AN - SCOPUS:0141485506
SN - 2162-237X
VL - 14
SP - 1217
EP - 1243
JO - IEEE Transactions on Neural Networks
JF - IEEE Transactions on Neural Networks
IS - 5
ER -