TY - GEN
T1 - When one should consider Schmitt trigger gates
AU - Beiu, Valeriu
AU - Ibrahim, Walid
AU - Tache, Mihai
AU - Kharbash, Fekri
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015
Y1 - 2015
N2 - This paper compares classical CMOS logic gates with their Schmitt trigger (ST) versions, when sized both conventionally as well as unconventionally. The reason for studying ST logic gates is due to their positive feedback which leads to hysteresis and, more importantly, to their better static noise margins (SNMs)-than classical CMOS logic gates. Obviously, the larger SNMs make ST logic gates less sensitive to noises and, hence, more reliable. While lately, quite a few papers have been looking at using ST design concepts for implementing more reliable SRAM bit cells, significantly less work has been targeting combinatorial logic. Here we are going to explore the whole voltage range and performance spectrum, for a better understanding of not only the SNMs and power consumptions (at different frequencies and voltage levels) of ST NAND-2 gate, but also of the delays (speeds) they could achieve. This should give a clearer picture of the advantages/disadvantages of ST for combinatorial logic in advanced CMOS technology nodes, and implicitly identify their application range.
AB - This paper compares classical CMOS logic gates with their Schmitt trigger (ST) versions, when sized both conventionally as well as unconventionally. The reason for studying ST logic gates is due to their positive feedback which leads to hysteresis and, more importantly, to their better static noise margins (SNMs)-than classical CMOS logic gates. Obviously, the larger SNMs make ST logic gates less sensitive to noises and, hence, more reliable. While lately, quite a few papers have been looking at using ST design concepts for implementing more reliable SRAM bit cells, significantly less work has been targeting combinatorial logic. Here we are going to explore the whole voltage range and performance spectrum, for a better understanding of not only the SNMs and power consumptions (at different frequencies and voltage levels) of ST NAND-2 gate, but also of the delays (speeds) they could achieve. This should give a clearer picture of the advantages/disadvantages of ST for combinatorial logic in advanced CMOS technology nodes, and implicitly identify their application range.
KW - CMOS
KW - Schmitt trigger
KW - logic gates
KW - power
KW - reliability
KW - sizing
KW - static noise margin (SNM)
UR - http://www.scopus.com/inward/record.url?scp=84964381130&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84964381130&partnerID=8YFLogxK
U2 - 10.1109/NANO.2015.7388698
DO - 10.1109/NANO.2015.7388698
M3 - Conference contribution
AN - SCOPUS:84964381130
T3 - IEEE-NANO 2015 - 15th International Conference on Nanotechnology
SP - 682
EP - 685
BT - IEEE-NANO 2015 - 15th International Conference on Nanotechnology
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th IEEE International Conference on Nanotechnology, IEEE-NANO 2015
Y2 - 27 July 2015 through 30 July 2015
ER -