This paper compares classical CMOS logic gates with their Schmitt trigger (ST) versions, when sized both conventionally as well as unconventionally. The reason for studying ST logic gates is due to their positive feedback which leads to hysteresis and, more importantly, to their better static noise margins (SNMs)-than classical CMOS logic gates. Obviously, the larger SNMs make ST logic gates less sensitive to noises and, hence, more reliable. While lately, quite a few papers have been looking at using ST design concepts for implementing more reliable SRAM bit cells, significantly less work has been targeting combinatorial logic. Here we are going to explore the whole voltage range and performance spectrum, for a better understanding of not only the SNMs and power consumptions (at different frequencies and voltage levels) of ST NAND-2 gate, but also of the delays (speeds) they could achieve. This should give a clearer picture of the advantages/disadvantages of ST for combinatorial logic in advanced CMOS technology nodes, and implicitly identify their application range.