XOR gates for low-energy and near-Vth operation

Azam Beg; Ajmal Beg; Amr Elchouemi

doi:10.1109/ICECS.2015.7440246

XOR gates for low-energy and near-V_th operation

Azam Beg, Ajmal Beg, Amr Elchouemi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

XOR gates are essential components of many logic circuits. With the aim of reducing energy dissipation, this paper proposes the use of genetic-algorithm-based optimization for XOR gates operating in the near-threshold region. We applied the proposed technique on four different types of XOR gates built using 22 nm devices. The resultant energy savings for the optimized gates ranged from 28% to 48% when compared with the traditionally-sized gates. The areas of the energy-optimized gates are also appreciably less than their conventional counterparts. The presented technique can be readily used for optimizing the gates for power, performance, noise-margin, etc.

Original language	English
Title of host publication	2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	49-52
Number of pages	4
ISBN (Electronic)	9781509002467
DOIs	https://doi.org/10.1109/ICECS.2015.7440246
Publication status	Published - Mar 23 2016
Event	IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015 - Cairo, Egypt Duration: Dec 6 2015 → Dec 9 2015

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	2016-March

Other

Other	IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015
Country/Territory	Egypt
City	Cairo
Period	12/6/15 → 12/9/15

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ICECS.2015.7440246

Cite this

Beg, A., Beg, A., & Elchouemi, A. (2016). XOR gates for low-energy and near-V_th operation. In 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015 (pp. 49-52). Article 7440246 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 2016-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.2015.7440246

XOR gates for low-energy and near-V_th operation. / Beg, Azam; Beg, Ajmal; Elchouemi, Amr.
2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015. Institute of Electrical and Electronics Engineers Inc., 2016. p. 49-52 7440246 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 2016-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Beg, A, Beg, A & Elchouemi, A 2016, XOR gates for low-energy and near-V_th operation. in 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015., 7440246, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 2016-March, Institute of Electrical and Electronics Engineers Inc., pp. 49-52, IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, 12/6/15. https://doi.org/10.1109/ICECS.2015.7440246

@inproceedings{dc0b72ff2aac449ca747895872289113,

title = "XOR gates for low-energy and near-Vth operation",

abstract = "XOR gates are essential components of many logic circuits. With the aim of reducing energy dissipation, this paper proposes the use of genetic-algorithm-based optimization for XOR gates operating in the near-threshold region. We applied the proposed technique on four different types of XOR gates built using 22 nm devices. The resultant energy savings for the optimized gates ranged from 28% to 48% when compared with the traditionally-sized gates. The areas of the energy-optimized gates are also appreciably less than their conventional counterparts. The presented technique can be readily used for optimizing the gates for power, performance, noise-margin, etc.",

author = "Azam Beg and Ajmal Beg and Amr Elchouemi",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015 ; Conference date: 06-12-2015 Through 09-12-2015",

year = "2016",

month = mar,

day = "23",

doi = "10.1109/ICECS.2015.7440246",

language = "English",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "49--52",

booktitle = "2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015",

}

TY - GEN

T1 - XOR gates for low-energy and near-Vth operation

AU - Beg, Azam

AU - Beg, Ajmal

AU - Elchouemi, Amr

PY - 2016/3/23

Y1 - 2016/3/23

N2 - XOR gates are essential components of many logic circuits. With the aim of reducing energy dissipation, this paper proposes the use of genetic-algorithm-based optimization for XOR gates operating in the near-threshold region. We applied the proposed technique on four different types of XOR gates built using 22 nm devices. The resultant energy savings for the optimized gates ranged from 28% to 48% when compared with the traditionally-sized gates. The areas of the energy-optimized gates are also appreciably less than their conventional counterparts. The presented technique can be readily used for optimizing the gates for power, performance, noise-margin, etc.

AB - XOR gates are essential components of many logic circuits. With the aim of reducing energy dissipation, this paper proposes the use of genetic-algorithm-based optimization for XOR gates operating in the near-threshold region. We applied the proposed technique on four different types of XOR gates built using 22 nm devices. The resultant energy savings for the optimized gates ranged from 28% to 48% when compared with the traditionally-sized gates. The areas of the energy-optimized gates are also appreciably less than their conventional counterparts. The presented technique can be readily used for optimizing the gates for power, performance, noise-margin, etc.

UR - http://www.scopus.com/inward/record.url?scp=84964853477&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84964853477&partnerID=8YFLogxK

U2 - 10.1109/ICECS.2015.7440246

DO - 10.1109/ICECS.2015.7440246

M3 - Conference contribution

AN - SCOPUS:84964853477

T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

SP - 49

EP - 52

BT - 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015

Y2 - 6 December 2015 through 9 December 2015

ER -